Method of manufacturing a flash memory device

专利摘要:
PURPOSE: A method for fabricating a flash memory cell is provided to improve a charge maintaining characteristic by preventing charges from being lost in the edge of a floating gate, and to decrease a repair rate by reducing a fail bit. CONSTITUTION: A tunnel oxide layer(23), the first polysilicon layer(24) and an oxide layer(25) are sequentially formed on a semiconductor substrate(21) having a field oxide layer(22). A predetermined region of the oxide layer, the first polysilicon layer and the tunnel oxide layer is etched to form a floating gate pattern. The second polysilicon layer is formed on the resultant structure and is blanket-etched to form a spacer on the sidewall of the first polysilicon layer. The oxide layer is removed. A dielectric layer(27), the third polysilicon layer(28), a tungsten silicide layer(29) and an anti-reflective coating(ARC)(30) are sequentially formed on the resultant structure. A predetermined region from the ARC to the tunnel oxide layer is etched to a stack gate in which a floating gate and a control gate are stacked. An impurity ion implantation process is performed regarding a predetermined region of the semiconductor substrate to form a source/drain region.
公开号:KR20020047511A
申请号:KR1020000075972
申请日:2000-12-13
公开日:2002-06-22
发明作者:박병수
申请人:박종섭；주식회사 하이닉스반도체；
IPC主号:

专利说明:

Method of manufacturing a flash memory device
[12] The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to form a floating gate pattern by patterning a first polysilicon layer so as to partially overlap an upper portion of a field oxide layer, and then forming a polysilicon spacer on a sidewall of the floating gate pattern. The present invention relates to a method of manufacturing a flash memory cell that can form a gently to prevent a charge loss phenomenon due to long concentration.
[13] 1 is a layout diagram of a state in which a stack gate of a typical flash memory cell is formed, and FIGS. 2 (a) and 2 (b) are diagrams of elements sequentially shown to explain a method of manufacturing a conventional flash memory cell. As sectional drawing, it is sectional drawing in the state cut along the AA 'line of FIG.
[14] 1 and 2 (a), field oxide films 2 and 12 are formed in a predetermined region on semiconductor substrates 1 and 11 by a general NSLOCOS process to determine active and field regions. After the tunnel oxide film 13 and the first polysilicon film 14 are formed on the entire structure, a lithography process and an etching process using a floating gate mask are performed to form the first polysilicon film 14 and the tunnel oxide film 13. Pattern. At this time, the first polysilicon film 14 is patterned so as to overlap a predetermined region of the field oxide films 2 and 12. The first polysilicon film 14 thus formed is sharply formed at an end portion by a step of the field oxide film 12 (A).
[15] Referring to FIGS. 1 and 2B, the dielectric film 15, the second polysilicon film 16, the tungsten silicide film 17, and the anti-reflection film 18 are sequentially formed on the entire structure. The lithography process and the etching process using the control gate mask are patterned from the antireflection film 18 to the tunnel oxide film 13 to form a stack gate structure in which the floating gate 3 and the control gate 4 are stacked. An impurity ion implantation process is then performed to form source and drain regions in the active region of the semiconductor substrate 11.
[16] When the flash memory cell is manufactured by the above process, the edge of the first polysilicon film overlapped with the field oxide film is sharply formed by the step of the lower field oxide film. When the floating gate of the flash memory cell is formed in this way, the field between the floating gate and the control gate is concentrated on the sharp part A of the floating gate by the gate stress generated in the flash memory cell after the cell is programmed. do. As a result, a charge loss phenomenon occurs in which the electrons stored in the floating gate escape to the control gate, and cause a malfunction of the device, such as having wrong data.
[17] SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a flash memory cell capable of preventing malfunction of a device by preventing concentration of fields at an edge portion of a floating gate formed to overlap a field oxide film.
[18] Another object of the present invention is to provide a method of manufacturing a flash memory cell that can prevent malfunction of a device by gently forming an edge portion of a floating gate formed to overlap with a field oxide film.
[19] In the present invention, the first polysilicon layer is patterned to partially overlap the field oxide layer to form a floating gate pattern, and then a polysilicon spacer is formed on the sidewalls of the floating gate pattern to smoothly form the edge portion of the floating gate, thereby causing loss of charge due to long concentration. Prevent the phenomenon.
[1] 1 is a cross-sectional view of a stack gate structure of a flash memory cell formed.
[2] 2 (a) and 2 (b) are cross-sectional views of devices sequentially shown for explaining a conventional method of manufacturing a flash memory cell.
[3] 3 (a) to 3 (d) are cross-sectional views of the elements shown in sequence for allowing a method of manufacturing a flash memory cell according to the present invention.
[4] <Explanation of symbols for the main parts of the drawings>
[5] 1, 11 and 21: semiconductor substrate 2, 12 and 22: field oxide film
[6] 3: floating gate 4: control gate
[7] 13 and 23: tunnel oxide film 14 and 24: first polysilicon film
[8] 15 and 27: dielectric film 16: second polysilicon film
[9] 17 and 29: tungsten silicide film 18 and 30: antireflection film
[10] 25 oxide film 26 second polysilicon spacer
[11] 28: third polysilicon film
[20] A method of manufacturing a flash memory cell according to the present invention includes the steps of sequentially forming a tunnel oxide film, a first polysilicon film and an oxide film on a semiconductor substrate on which a field oxide film is formed, and the predetermined method of the oxide film, the first polysilicon film and the tunnel oxide film. Etching a region to form a floating gate pattern, forming a second polysilicon film on the entire structure, and then performing a front etching process to form a spacer on sidewalls of the first polysilicon film; and removing the oxide film. And sequentially forming a dielectric film, a third polysilicon film, a tungsten silicide film, and an anti-reflection film on the entire structure, and etching a predetermined region from the anti-reflection film to the tunnel oxide film to stack the floating gate and the control gate. Forming a stack gate and removing impurities from a predetermined region of the semiconductor substrate; Performing implantation process will be characterized by comprising a step of forming the source and drain regions.
[21] Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
[22] FIG. 1 is a layout after forming a stack gate of a flash memory cell, and FIGS. 3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing a flash memory cell according to the present invention. It is sectional drawing of the state cut along the AA 'line of FIG.
[23] 1 and 3 (a), field oxide films 2 and 22 are formed in a predetermined area on semiconductor substrates 1 and 21 by a general NSLOCOS process to determine active and field areas. The tunnel oxide film 23 and the first polysilicon film 24 are formed on the entire structure. An oxide film 25 is formed on the first polysilicon film 24. Here, the oxide film 25 is deposited using a CVD method, or the first polysilicon film 24 is oxidized to form a thickness of about 30 to 200 Å. Instead of the oxide film 25, a nitride film may be formed.
[24] Referring to FIGS. 1 and 3B, an oxide layer 25, a first polysilicon layer 24, and a tunnel oxide layer 23 are patterned by performing a lithography process and an etching process using a floating gate mask. In this case, the first polysilicon film 24 is patterned so as to overlap in a predetermined region above the field oxide films 2 and 22.
[25] Referring to FIG. 3C, after forming the second polysilicon layer on the entire structure, the spacer 26 is formed on the sidewalls of the first polysilicon layer pattern by performing an entire surface etching process. The second polysilicon film is formed thicker or thinner by about 100 microseconds than the first polysilicon film 24. At this time, the oxide film 25 serves to prevent the first polysilicon film 24 from being damaged in the process of etching the second polysilicon film 26 due to the difference in the etching ratio between the oxide film and the polysilicon film. If the etching process is performed without forming the oxide layer 25, the first polysilicon layer 24 may be damaged, thereby deteriorating characteristics of the floating gate, thereby causing a problem in charge retention. In addition, the transient etching process for forming the spacer 26 is adjusted so that the spacer 26 is formed by the height of the pattern of the first polysilicon film 24.
[26] 1 and 3 (d), after the oxide film 25 is removed by a cleaning process, the dielectric film 27, the third polysilicon film 28, the tungsten silicide film 29, and the anti-reflection film are formed on the entire structure. 30 is formed sequentially. The lithography process and the etching process using the control gate mask are patterned from the anti-reflection film 30 to the tunnel oxide film 22 to form a stack gate structure in which the floating gate 3 and the control gate 4 are stacked. Thereafter, an impurity ion implantation process is performed on the semiconductor substrate 21 in the active region to form a source and a drain region.
[27] As described above, according to the present invention, it is possible to prevent charge loss that may occur at the edge portion of the floating gate, thereby improving charge retention characteristics, and reducing a fail bit by reducing a fail bit. Therefore, the yield of the device can be improved. In addition, by forming the buffer oxide layer, damage to the floating gate generated during the entire etching process may be prevented, thereby maintaining the characteristics of the floating gate.

权利要求:
Claims (6)
[1" claim-type="Currently amended] Sequentially forming a tunnel oxide film, a first polysilicon film, and an oxide film on the semiconductor substrate on which the field oxide film is formed;
Etching a predetermined region of the oxide film, the first polysilicon film, and the tunnel oxide film to form a floating gate pattern;
Forming a spacer on the sidewalls of the first polysilicon film by forming a second polysilicon film on the entire structure and then performing an entire etching process;
Removing the oxide film and sequentially forming a dielectric film, a third polysilicon film, a tungsten silicide film, and an anti-reflection film on the entire structure;
Etching a predetermined region from the anti-reflection film to the tunnel oxide film to form a stack gate in which a floating gate and a control gate are stacked;
And forming a source and a drain region by performing an impurity ion implantation process on a predetermined region of the semiconductor substrate.
[2" claim-type="Currently amended] The method of claim 1, wherein the oxide film is formed by deposition using a CVD method or by oxidizing the first polysilicon film.
[3" claim-type="Currently amended] The method of manufacturing a flash memory cell according to claim 1, wherein a nitride film is formed instead of the oxide film.
[4" claim-type="Currently amended] The method of claim 1, wherein the oxide film and the nitride film are formed to have a thickness of 30 to 200 microseconds, respectively.
[5" claim-type="Currently amended] The method of claim 1, wherein the floating gate pattern is formed to overlap a predetermined region with the field oxide layer.
[6" claim-type="Currently amended] The method of claim 1, wherein the second polysilicon film is formed to be 100 kHz thicker or thinner than the first polysilicon film.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2000-12-13|Application filed by 박종섭, 주식회사 하이닉스반도체

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2000-12-13|Priority to KR1020000075972A

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2002-06-22|Publication of KR20020047511A

优先权:

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申请号 | 申请日 | 专利标题

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KR1020000075972A|KR20020047511A|2000-12-13|2000-12-13|Method of manufacturing a flash memory device|